1. Field of the Invention
The present invention generally relates to computer systems, particularly to a method of maintaining cache coherency in a multi-processor computer system, while allowing the posting of certain cache operations such that a broadcast of an operation may be delayed but the operation may nevertheless execute immediately, and further relates to more efficient handling of such posted operations.
2. Description of Related Art
The basic structure of a conventional multi-processor computer system 10 is shown in FIG. 1. Computer system 10 has several processing units, two of which 12a and 12b are depicted, which are connected to various peripheral devices, including input/output (I/O) devices 14 (such as a display monitor, keyboard, and permanent storage device), memory device 16 (such as random access memory or RAM) that is used by the processing units to carry out program instructions, and firmware 18 whose primary purpose is to seek out and load an operating system from one of the peripherals (usually the permanent memory device) whenever the computer is first turned on. Processing units 12a and 12b communicate with the peripheral devices by various means, including a generalized interconnect or bus 20. Computer system 10 may have many additional components which are not shown, like serial and parallel ports for connection to modems or printers. Those skilled in the art will further appreciate that there are other components that might be used in conjunction with those shown in the block diagram of FIG. 1; a display adapter might be used to control a video display monitor, a memory controller can be used to access memory 16, etc. The computer can also have more than two processing units.
In a symmetric multi-processor (SMP) computer, all of the processing units are generally identical, that is, they all use a common set or subset of instructions and protocols to operate, and generally have the same architecture. A typical SMP architecture is shown in FIG. 1. A processing unit includes a processor core 22 having a plurality of registers and execution units, which carry out program instructions in order to operate the computer. An exemplary processing unit includes the PowerPC.TM. processor marketed by International Business Machines Corp. The processing unit can also have one or more caches, typically an instruction cache 24 and a data cache 26, which are implemented using high speed memory devices. Caches are commonly used to temporarily store values (instructions and/or data) that might be repeatedly accessed by a processor, in order to speed up processing by avoiding the longer step of loading the values from memory 16. These caches are referred to as "on-board" when they are integrally packaged with the processor core on a single integrated chip 28. Each cache is associated with a cache controller (not shown) that manages the transfer of data between the processor core and the cache memory.
A processing unit can include additional caches, such as cache 30, which is referred to as a level 2 (L2) cache since it supports the on-board (level 1) caches 24 and 26. In other words, cache 30 acts as an intermediary between memory 16 and the on-board caches, and can store a much larger amount of information (instructions and data) than the on-board caches can, but at a longer access penalty. Cache 30 may be a chip having a storage capacity of 256 or 512 kilobytes, while the processor may be an IBM PowerPC.TM. 604-series processor having on-board caches with 64 kilobytes of total storage. Cache 30 is connected to bus 20, and all loading of information from memory 16 into processor core 22 must come through cache 30. Although FIG. 1 depicts only a two-level cache hierarchy, multi-level cache hierarchies can be provided where there are many levels (L3, L4, etc.) of serially connected caches.
In an SMP computer, it is important to provide a coherent memory system, that is, to cause write operations to each individual memory location to be serialized in some order for all processors. Assuming that a location in memory is modified by a sequence of write operations to take on the specific successive values of "1," "2," "3," and "4," in a cache coherent system all processors will observe the writes to the given location to take place in the order shown. However, it is possible for a processing element to miss a write to the memory location. A given processing element reading the memory location could see the sequence 1, 3, 4, missing the update to the value 2. A system that implements these properties is said to be "coherent". Virtually all coherency protocols operate only to the granularity of the size of a cache block. That is to say, the coherency protocol controls the movement of and write permissions for data on a cache block basis and not separately for each individual memory location.
There are a number of protocols and techniques for achieving cache coherence that are known to those skilled in the art. At the heart of all these mechanisms for maintaining coherency is the requirement that the protocols allow only one processor to have a "permission" that allows a write to a given memory location (cache block) at any given point in time. As a consequence of this requirement, whenever a processing element attempts to write to a memory location, it must first inform all other processing elements of its desire to write the location and receive permission from all other processing elements to carry out the write. The key issue is that all other processors in the system must be informed of the write by the initiating processor before the write occurs. Furthermore, if a block is present in the L1 cache of a given processing unit, it is also present in the L2 and L3 caches of that processing unit. This property is known as inclusion.
To implement cache coherency in a system, the processors communicate over a common generalized interconnect (i.e., bus 20). The processors pass messages over the interconnect indicating their desire to read or write memory locations. When an operation is placed on the interconnect, all of the other processors "snoop" (monitor) this operation and decide if the state of their caches can allow the requested operation to proceed and if so, under what conditions. There are several bus transactions that require snooping and follow-up action to honor the bus transactions and maintain memory coherency. The snooping operation is triggered by the receipt of a qualified snoop request, generated by the assertion of certain bus signals. Instruction processing is interrupted only when a snoop hit occurs and the snoop state machine determines that an additional cache snoop is required to resolve the coherency of the offended sector.
This communication is necessary because, in systems with caches, the most recent valid copy of a given block of memory may have moved from the system memory 16 to one or more of the caches in the system (as mentioned above). If a processor (say 12a) attempts to access a memory location not present within its cache hierarchy, the correct version of the block, which contains the actual (current) value for the memory location, may either be in the system memory 16 or in one of more of the caches in another processing unit, such as processing unit 12b. If the correct version is in one or more of the other caches in the system, it is necessary to obtain the correct value from the cache(s) in the system instead of system memory.
For example, consider a processor, say 12a, attempting to read a location in memory. It first polls its own L1 cache (24 or 26). If the block is not present in the L1 cache, the request is forwarded to the L2 cache (30). If the block is not present in the L2 cache, the request is forwarded on to lower cache levels, like the L3 cache. If the block is not present in the lower level caches, the request is then presented on the generalized interconnect (20) to be serviced. Once an operation has been placed on the generalized interconnect, all other processing units snoop the operation and determine if the block is present in their caches. If a given processing unit has the block of data requested by processing unit in its L1 cache, and that data is modified, by the principle of inclusion the L2 cache and any lower level caches also have copies of the block (however, their copies are stale, since the copy in the processor's cache is modified). Therefore, when the lowest level cache (e.g., L3) of the processing unit snoops the read instruction, it will determine that the block requested is present and modified in a higher level cache. When this occurs, the L3 cache places a message on the generalized interconnect informing the processing unit that it must "retry" its operation again at a later time, because the actual value of the memory location is in the L1 cache at the top of the memory hierarchy and must be retrieved to make it available to service the read request of the initiating processing unit.
Once the request from an initiating processing unit has been retried, the L3 cache begins a process to retrieve the modified data from the L1 cache and make it available at the L3 cache, main memory or both, depending on the exact details of the implementation which are not specifically relevant to this invention. To retrieve the block from the higher level caches, the L3 cache sends messages through the inter-cache connections to the higher level caches, requesting that the block be retrieved. These messages propagate up the processing unit hierarchy until they reach the L1 cache and cause the block to be moved down the hierarchy to the lowest level (L3 or main memory) to be able to service the request from the initiating processing unit.
The initiating processing unit eventually re-presents the read request on the generalized interconnect. At this point, however, the modified data has been retrieved from the L1 cache of a processing unit and the read request from the initiating processor will be satisfied. The scenario just described is commonly referred to as a "snoop push". A read request is snooped on the generalized interconnect which causes the processing unit to "push" the block to the bottom of the hierarchy to satisfy the read request made by the initiating processing unit.
The essential point is that, when a processor wishes to read or write a block, it must communicate that desire with the other processing units in the system in order to maintain cache coherence. To achieve this, the cache coherence protocol associates with each block in each level of the cache hierarchy, a status indicator indicating the current "state" of the block. The state information is used to allow certain optimizations in the coherency protocol that reduce message traffic on the generalized interconnect and the inter-cache connections. As one example of this mechanism, when a processing unit executes a read it receives a message indicating whether or not the read must be retired later. If the read operation is not retried, the message usually includes information allowing the processing unit to determine if any other processing unit also has a still active copy of the block (this is accomplished by having the other lowest level caches give a "shared" or "not shared" indication for any read they do not retry). Therefore, a processing unit can determine whether any other processor in the system has a copy of the block. If no other processing unit has an active copy of the block, the reading processing unit marks the state of the block as "exclusive". If a block is marked exclusive it is permissible to allow the processing unit to later write the block without first communicating with other processing units in the system because no other processing unit has a copy of the block. Therefore, it is possible for a processor to read or write a location without first communicating this intention onto the interconnection, but only where the coherency protocol has insured that no other processor has an interest in the block.
The foregoing cache coherency technique is implemented in one prior art protocol referred to as "MESI," and illustrated in FIG. 2. In this protocol, a cache block can be in one of four states, "M" (Modified), "E" (Exclusive), "S" (Shared) or "I" (Invalid). Under the MESI protocol, each cache entry (e.g., a 32-byte sector) has two additional bits which indicate the state of the entry, out of the four possible states. Depending upon the initial state of the entry and the type of access sought by the requesting processor, the state may be changed, and a particular state is set for the entry in the requesting processor's cache.
When a block is in the Modified state, the addressed block is valid only in the cache having the modified block, and the modified data has not been written back to system memory. When a block is Exclusive, it is present only in the noted block, and is consistent with system memory. If a block is Shared, it is valid in that cache and in at least one other cache, all of the shared blocks being consistent with system memory. Finally, when a block is Invalid, it means that any resident value is not valid with respect to any corresponding address indicated for the block, i.e., the value is not consistent with system memory. As seen in FIG. 2, if a block is in any of the Modified, Shared or Invalid states, it can move between the states depending upon the particular bus transaction. While a block in an Exclusive state can move to any other state, a block can only become Exclusive if it is first Invalid. A cache's block can become Invalid (e.g., from the Shared state) if the cache snoops an operation from a different processor indicating that the value held in the cache block is to be modified by the other processor, such as by snooping a read-with-intent-to-modify (RWITM) operation.
Some processor architectures, including the PowerPC.TM. processor, allow the execution of one or more special operations, other than the RWITM operation, when a processor wants to claim a memory block for a future store instruction (modifying the block). The "DClaim" operation is one example. This operation is used in lieu of the RWITM bus transaction when a valid value for the subject block is already held in the same processor's cache, e.g., in a Shared state (if the value were currently held in a Modified or Exclusive state, there would be no need to broadcast either a RWITM or DClaim request since the processor would already have exclusive control of the block). The processor may be adapted to execute a DClaim operation initially, by examining its on-board (L1) cache to see if the valid value is resident there. If not, the processor can issue a RWITM request, and any lower level cache having the valid value will, upon receiving the RWITM request, convert it into a DClaim operation to be passed to the system bus. The DClaim operation accordingly is an address-only operation since the value does not need to be read (from system memory or any intervening cache). Because of this attribute, the DClaim operation is more efficient than a RWITM operation, which would force the read operation across the system bus. When another cache has the same addressed block in a valid (Shared) state and snoops a DClaim transaction for the block, that other cache switches its corresponding block to an Invalid state, releasing the block so that the requesting processor can proceed to modify the value. In other words, a DClaim transaction appears just like a RWITM operation from a snooper perspective.
One problem with DClaim-type operations is that they occasionally (sometimes frequently) suffer significant performance degradation, since completion of the operation can be delayed by coherency responses from other devices in the memory hierarchy. For example, if several caches of different processing units are holding a value in Shared states and they snoop a DClaim operation, their respective processors may repeatedly issue retry messages in response to the DClaim snoop (if these processors are currently busy or otherwise unable to handle the snoop, for whatever reason). This outcome means that the processor of the cache issuing the DClaim request must effectively halt processing of the associated program instruction set (an instruction "thread"), since the processor cannot complete the desired store of the modified value until the DClaim request is re-issued, possibly repeatedly, and appropriate (non-retry) responses are received from all other caches. A significant delay might also occur due to the operation having to wait in line in the cache operation queue.
The same problems can occur with a typical RWITM operation, but with a DClaim operation it might actually be unnecessary to wait to execute the DClaim store. Every other cache (including those responding with "retry") must have the targeted block in either the Invalid state or the Shared state. If the cache block were Invalid, then the eventual response ("null" or "clean") would not interfere with the operation. If the cache block were Shared, and presuming that none of the other processors were contemporaneously issuing DClaim requests for the same block, it would be unnecessary for the initiating processor to wait to execute the DClaim store instruction, since no other action would be required of the responding caches before the DClaim operation could properly complete. Unfortunately, the prior art does not provide any method of knowing or ensuring that no other Shared cache blocks are attempting to execute conflicting DClaim operations at approximately the same time.
If two or more caches hold a value in the Shared state and they do issue DClaim requests simultaneously or nearly simultaneously (i.e., they attempt to cross-invalidate each other), then a deadlock can occur wherein each associated processor becomes ensnared in an endless cycle of retry responses. One method for handling such pipeline collisions is to modify the coherency protocol to preclude a cache from issuing a retry response to a DClaim request if that cache itself has an outstanding DClaim request for the same block and a response to the latter request has not been received yet. In other words, if a cache having a Shared block has issued a DClaim request and has not yet received appropriate responses allowing completion of the store instruction, and it snoops a second DClaim request from another cache for the same block, then it must not retry the second Dclaim until it has received null responses for its own request.
These problems can be especially acute where the processing environment is such that a significant number of memory blocks end up getting shared among at least two processors. Other factors can compound the problems, such as when the processing system allows read-write operations to be atomized using load-and-reserve instructions (in the PowerPC.TM. instruction set, "lwarx" for 32-bit implementations and "ldarx" for 64-bit implementations) followed by associated conditional store instructions ("stwcx" for 32-bit implementations and "stdcx" for 64-bit implementations). The conditional store instructions can result in delayed DClaim operations, possibly nullifying the benefits of attempting to atomize the read-write operation.
The foregoing problems are also exacerbated by the fact that it might be unnecessary to broadcast a DClaim request (and therefore unnecessary to handle subsequent responses and replies). An example is the eviction of the value from the cache of the processor which issued a particular DClaim operation, as described above, that does not require waiting for responses. An eviction can result when the processor executes other instructions from other threads, such that other unrelated values must be loaded in the cache and displace (cast out) one or more existing blocks. The eviction algorithm, such as a least recently used (LRU) algorithm, might pick a block for eviction that is the subject of a recent DClaim operation. The block may be cast out in a burst write operation. In such cases (and again presuming that none of the other processors were contemporaneously issuing DClaim requests for the same block), the DClaim operation becomes extraneous, since the write operation would be broadcast to any other caches having the Shared value, and so those other cache blocks would switch to Invalid anyway. Conventional cache coherency protocols cannot eliminate such redundant broadcasts.
In light of the foregoing problems, it would be desirable to provide a method of handling DClaim-type operations which did not require an initiating processor to wait for unnecessary cache responses. It would be further advantageous if the method could avoid deadlocks without losing the benefits of the DClaim operation, or could eliminate unnecessary DClaim operations which had become moot as a result of intervening events.